In response to an increased need for smaller electronic devices with denser circuits, devices with three-dimensional (3D) structures have been developed. An example of such devices includes FinFET devices having conductive fin-like structures that are raised vertically above the horizontally extending substrate. Referring to FIG. 1, there is shown a perspective view of a conventional FinFET device 100 formed on a substrate 102. The substrate 102 may comprise, for example, a silicon substrate. On the substrate 102, there may be an oxide layer 104. This oxide layer 104 may be, for example, silicon oxide. FinFET device 100 may also comprise a fin structure 106 which may serve as a source, drain, and a channel. The conventional FinFET device 100 may also include a gate 112 formed across the fin structure 106, and a gate dielectric 108 that electrically isolates the gate 112 from the fin structure 106. In the conventional FinFET device 100, the surface area of the fin structure 106 in contact with gate dielectric 108 may be the effective channel region.
Much like other conventional MOS devices, FinFET device 100 also comprises spacers 122 disposed on selected regions of the FinFET device 100. Generally, the spacers 122 are dielectric materials formed on the vertical side surfaces of the gate 112, as illustrated in FIG. 2. These are formed by depositing a dielectric material, such as, for example, silicon nitride, on gate 112 and the fin structure 106 and selectively removing material from the fin structure 106. In particular, the dielectric material is deposited on the side surfaces 112a and top surface 112b of the gate 112, and on the side surfaces 106a and top surface 106b of the fin structure 106. Thereafter, the dielectric material is removed from the side surfaces 106a and top surface 106b of the fin structure 106. The dielectric material may also be removed from the top surface 112b of the gate 112, thereby leaving dielectric material only on the side surfaces 112a of the gate 112a. 
If improperly formed, the spacers 122 may adversely affect the performance of the FinFET device 100. In the conventional method, the dielectric material may be overetched, and the resulting spacers 122 may provide inadequate coverage of the side surfaces 112a of the gate 112. In addition, the spacer residue 124 may be left on the side surfaces 106a of the fin structure 106. The spacers 122 with inadequate coverage, or spacer residue 124 near the fin structure 106 may detrimentally affect the performance of the FinFET device 100. To compensate, the gate 112 is formed much taller than the fin structure 106, and the fin structure 106 is formed tapered to enhance removal of the dielectric material from the fin structure 106. This results in a tapered fin structure 106 which degrades short channel effects. It also results in some non-uniformity of the spacer width due to overetch. Accordingly, a new method for forming FinFET device is needed.